A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. Such subsystems are commonly implemented as either removable memory cards that can be inserted into multiple host systems or as non-removable embedded storage within the host system. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash EEPROM devices are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. A typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks, wherein a block contains the smallest number of cells (unit of erase) that are erasable at one time.
In one commercial form, each block contains enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it is stored. The amount of user data included in a sector is the standard 512 bytes in one class of such memory systems but can be of some other size. Because the isolation of individual blocks of cells from one another that is required to make them individually erasable takes space on the integrated circuit chip, another class of flash memories makes the blocks significantly larger so there is less space required for such isolation. But since it is also desired to handle user data in much smaller sectors, each large block is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data. Each page usually stores one sector of user data, but a page may store a partial sector or multiple sectors. A “sector” is used herein to refer to an amount of user data that is transferred to and from the host as a unit.
The subsystem controller in a large block system performs a number of functions including the translation between logical addresses received by the memory sub-system from a host, and physical addresses within the memory cell array. This translation often involves use of intermediate terms for a logical block number (LBN) and logical page. The controller also manages the low-level flash circuit operation through a series of commands that it issues to the flash memory devices via an interface bus. Another function the controller performs is to maintain the integrity of data stored to the subsystem through various means, such as by using an error correction code (ECC).
In case of a power outage during operation of such a memory circuit, for example if a memory card is removed from a host or a power is lost to a device with an integrated memory, the memory may be caught in the middle of a write or erase operation, resulting in an incomplete operation. For example, if a memory system loses power during a programming process when most, but not all, of the cells in a group being written have reached their target state, the write group may contain a large number of errors. As is familiar in the art, it is common to incorporate error correction code (ECC) into memory systems to determine and correct data errors. A power outage before completion of a programming operation can cause the write group to be in three situations when the interrupted write group is read: (1) it is correctable by ECC; (2) it is uncorrectable by ECC; and (3) an ECC mis-detect can occur. In the first case, the extent of the error is minor enough where the error correction code can salvage the data. In the second case, the data will be incorrect, but the system will determine this condition. In the third case, the data will again be incorrect, but, due to an ECC mis-detect, the system is unaware of the situation.
This last case, the ECC mis-detect, can occur if, for example, the ECC has the capacity to correct up to, say, 4 bits of error, but 7 bits of data in the write group were not correctly written. The system will then unaware of the incorrectly written data and operate as if it has corrected any error in the write group, but the data will still be wrong. A similar situation can occur if power loss occurs during an erase process. These scenarios make ECC write and erase abort detection far from perfect and are particularly troublesome for mission critical situations where it is important to know if the data has been correctly entered. Consequently, there is room for improvement in this aspect of memory systems.